1. Field of the Invention
The present invention relates to a ferroelectric memory device which employs a ferroelectric capacitor and a transfer gate as a memory cell.
2. Description of the Related Art
Since an electric charge accumulated at a plate electrode pair of a capacitor is retained by spontaneous polarization of a ferroelectric, the ferroelectric memory device is nonvolatile and does not require any refreshing operation. There are two types of ferroelectric memory cell, one has a ferroelectric capacitor instead of a paraelectric capacitor connected to a transfer gate in series, and the other has a ferroelectric in stead of a paraelectric between a floating gate and a control gate of an EPROM transistor.
In the latter type of ferroelectric memory device, such one is disclosed (Japanese Laid-open Patent Publication No. 8-235872), in which write transistors are coupled between the respective floating gates and bit lines in order to erase memory cell contents row by row with the write transistors turning on row by row. However, in the former ferroelectric memory device, no construction for collectively erasing is disclosed at all.
FIG. 12 shows a schematic construction of a prior-art ferroelectric memory device. In FIG. 12, a 2.times.2 memory cell array is shown for simplification.
In a memory cell 10, one plate electrode of a ferroelectric capacitor 11 is connected via a transfer gate 12 to a bit line BL0, and the other plate electrode of the ferroelectric capacitor 11 is connected to a plate line PL0. A voltage applied to the ferroelectric capacitor 11 in the direction of an arrow illustrated in FIG. 12 is denoted as VF, and the positive direction of a dielectric polarization P of the ferroelectric in the ferroelectric capacitor 11 is assumed to be the direction of another arrow illustrated in FIG. 12. The memory cell content of the memory cell 10 is defined as "0" when the dielectric polarization P is the positive direction at VF=0.
Operation of the ferroelectric memory device is similar to those of a DRAM.
(1) A read operation for the memory cell 10 in which "1" is stored
Referring to FIG. 13, a description will be given of the read operation for the memory cell 10 in which "1" is stored. Each hysteresis loop in FIG. 13 is the same and it denotes the relationship between electric field intensity E applied to the ferroelectric in the capacitor 11 with voltage VF and dielectric polarization P. The black dots show states (E, P) at respective time.
At a time t0, a word line WL0 and the plate line PL0 are low, the transfer gate 12 is off, and the ferroelectric is at a state S00. Further, a potential of a pair of complementary bit lines BL0 and *BL0 is reset at 0V by a bit line reset circuit 20. Furthermore, a sense amplifier 21 is inactive.
A control circuit 22 generates various control signals on the basis of a row address strobe signal *RAS, a column address strobe signal *CAS, and a write enable signal *WE ("*" denotes that its signal is low active), which are from the exterior. An address ADR is provided to a row address buffer register 23, the control circuit 22 provides a latch signal to the clock input of the row address buffer register 23 in response to a fall of the row address strobe signal *RAS, and causes the bit line reset circuit 20 to finish the resetting.
The output of the row address buffer register 23 is decoded by a row decoder 24, and the word line WL0 and the plate line PL0 rise at a time t1 when a timing signal provided from the control circuit 22 to the row decoder 24 becomes active.
When a content of the memory cell 10 connected to the bit line BL0 is read, a dummy word line DWL0 is raised in order to cause a dummy cell 30, which is connected to the bit line *BL0 complementary to the bit line BL0, to output the content thereof at the same time the word line WL0 rises. To the contrary, when reading a content of a memory cell connected to the bit line *BL0, a dummy word line DWL1 is raised in order to cause a dummy cell 31 connected to the bit line BL0 to output a content thereof at the same time when the word line WL0 rises.
The transfer gate 12 is turned on by a rise of the word line WL0, and a positive charge is pushed out from the ferroelectric capacitor 11 by a rise of the plate line PL0, whereby a positive charge flows via the transfer gate 12 to the bit line BL0 to cause the bit line BL0 to rise a little.
Simultaneously, a positive charge flows from the dummy cell 30 to the bit line *BL0, and the amount thereof is smaller than that from a memory cell in which "1" is stored, but greater than that from a memory cell in which "0" is stored. Thereby, the potential difference between the bit line pair BL0 and *BL0 arise. The voltage VF applied to the ferroelectric which is almost equal to the potential difference between the plate line PL0 and the bit line BL0 becomes positive by a rise of the plate line PL0, the dielectric polarization P is reversed, and the ferroelectric is turned into a state S01.
Next, at a time t2, the sense amplifier 21 is activated by a signal coming from the control circuit 22, and the potential difference is amplified, whereby the voltage VF becomes zero. The ferroelectric enters into a state S02 with spontaneous polarization.
An address ADR is provided to a column address buffer register 33. The control circuit 22 provides a latch pulse to the clock input of the column address buffer register 33 in response to a fall of the column address strobe signal *CAS. The output of the column address buffer register 33 is decoded by a colum decoder 34, and the column selection line CSL0 is caused to rise by a timing signal from the control circuit 22 at a time t3, whereby a column gate 35 is turned on, the signal on the bit lines BL0 and *BL0 goes through the column gate 35 to data bus lines DB and *DB, and are amplified and retained by an I/O buffer circuit 36, from which the signal is outputted as DATA.
At a time t4, the potential of the plate line PL0 is caused to fall by a timing signal from the control circuit 22 to the row decoder 24, whereby the voltage VF becomes negative to cause the spontaneous polarization to be reversed, and the ferroelectric is turned from the state S03 into a state S04.
At a time t5, on one hand, potentials of the word line WL0 and dummy word line DWL0 are caused to fall by a timing signal from the control circuit 22 to the row decoder 24, and on the other hand, the sense amplifier 21 becomes inactive by a signal from the control circuit 22 to the sense amplifier 21. Thereby, a potential of the bit line BL0 falls, the voltage VF returns to 0V, and the ferroelectric enters into the state S05 which is the same as the initial state S00.
(2) A read operation for the memory cell 10 in which "0" is stored.
If "0" is stored in the memory cell 10 at the time t0, the potential of the bit line BL0 is lower than that of the bit line *BL0 at the time t2. Therefore, the bit line BL0 becomes low with the activation of the sense amplifier 21, and the voltage VF is further raised, and next, the potential VF falls to 0V with a fall of the potential of the plate line PL0 at the time t4. Since the voltage VF has only a positive pulse, after a read operation has finished, the memory cell 10 becomes the original state where "0" is stored.
(3) WRITE operation of "0" for the memory cell 10
FIG. 14 are time charts showing operation of writing "0" into the memory cell 10 in which "1" has been stored. The operation from the time t0 to t3 is the same as those from the time t0 to t3 in FIG. 13.
At the time t3, a write enable signal WE rises in response to a fall of the write enable signal *WE, whereby writing control is commenced. At the time t3, the column gate 35 is turned on, whereby low and high writing potentials on the data bus lines DB and *DB go through the column gate 35 onto the bit lines BL0 and *BL0, respectively. Thereby, the voltage VF is caused to rise, and the ferroelectric enters into a state S13.
At the time t4, the plate line PL0 falls, and the voltage VF falls to 0V. The ferroelectric enters into a state S14 with spontaneous polarization, and the memory cell 10 becomes a state "0".
At the time t5, the potentials of the word line WL0 and the dummy word line DWL0 are caused to fall. In addition, the sense amplifier 21 becomes inactive. Thereby, the potential of the bit line *BL0 falls. The voltage VF remains at 0V, and the ferroelectric is in the state S15 which is the same as the state S14.
(4) WRITE operation of "1" for the memory cell 10
When writing "1" into the memory cell 10, the potentials of the bit lines BL0 and *BL0 do not change at the time t3 in FIG. 14. Next, the voltage VF falls at the time t4 as the same as in FIG. 13. Next, the voltage VF returns to 0V at the time t5 as the same as in FIG. 13. Thus, the memory cell 10 becomes a state "1".
FIG. 15 shows a schematic construction of another prior-art ferroelectric memory device.
In the device, a pair of memory cells 10 and 10A are employed to store 1 bit, instead of using the dummy cell 30 shown in FIG. 12. And, by writing complementary values in the memory cells 10 and 10A, the potential difference between the bit line pair BL0 and *BL0 is made greater than in the case of FIG. 12 when reading out.
Since ferroelectric memory devices are non-volatile and easy to write, they can be used for IC cards to handle electronic cash in banks, etc. In this case, erasing of the memory contents only in a software manner is not sufficient in view of security, therefore it is necessary to erase the memory contents in a hardware manner.
However, since, in the above described prior-art ferroelectric memory device, the memory contents must be erased bit by bit with repeating normal writing operation, the time required for erasing becomes longer, resulting in an increase in consumption power. The problem becomes more serious with an increase in memory capacity.